DocumentCode :
2910647
Title :
Automated test pattern generation for VHDL codes of VLSI chips
Author :
Dobson, Kevin G. ; Brooks, Euclid S.
Author_Institution :
Dept. of Electr. Eng., Howard Univ., Washington, DC, USA
fYear :
1998
fDate :
24-27 Aug 1998
Firstpage :
665
Abstract :
Summary form only given, as follows. This paper introduces a methodology for automated test pattern generation (ATPG) for VHDL codes of VLSI chips. A VHDL specification of a VLSI chip can be modeled as a data flow graph based EFSM (Extended Finite State Machine). The EFSM model is then checked for any of the three types of defined consistencies. Techniques available for finite state machines (FSM) testing can then be used to generate test patterns for the consistent EFSM model (with all inconsistencies detected and removed). Algorithms are being developed and coded for detection and removal of inconsistencies and for optimized test pattern generation for the consistent EFSM. Examples are used to introduce and explain the processes, algorithms and tools used in this project
Keywords :
VLSI; automatic test pattern generation; data flow graphs; finite state machines; hardware description languages; integrated circuit testing; logic testing; ATPG; DFG; FSM testing; VHDL codes; VHDL specification; VLSI chips; automated test pattern generation; data flow graph; extended FSM; extended finite state machine; Automata; Automatic test pattern generation; Computer architecture; Educational institutions; Flow graphs; Test pattern generators; Testing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
AUTOTESTCON '98. IEEE Systems Readiness Technology Conference., 1998 IEEE
Conference_Location :
Salt Lake City, UT
ISSN :
1088-7725
Print_ISBN :
0-7803-4420-0
Type :
conf
DOI :
10.1109/AUTEST.1998.713514
Filename :
713514
Link To Document :
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