CMOS Nanostructure with Auto-Programmable Thermal Loop and Superior-Order Curvature Corrected Technique

A new auto-programmable superior-order curvature-corrected integrated nanostructure will be presented, based on the compensation of the gate-source voltage temperature nonlinearity by a suitable biasing of a MOS transistor at a PTAT current. In order to maximize the temperature behavior of the system, a thermal stabilization circuit and an auto-programmable loop will be designed to select the optimal values for the chip temperature 7q and for the value of parameter a (equivalent to select the optimal type of the curvature-correction technique). Because these optimal values of a and 7q are determined using a previous stored data basis referring to the nanostructure circuit behavior, the errors caused by the finite precision of parameters determination will be cancel out.