Automated translation of ASIC designs

Summary form only given, as follows. Tremendous advances in application specific integrated circuit (ASIC) technology are continually being made in speed, power, and gate density. This paper discusses the development of an automated translation process that allows the advances in ASIC technology to be applied to existing ASIC designs without having to redesign the ASICs. This translation process is accomplished by replacing an existing design with a functionally equivalent design that is created to take advantage of the advances in ASIC technologies. The translation process makes use of various HDL (Hardware Design Language) based computer tools, old and new technology libraries, and VHDL (Very High Speed Integrated Circuit HDL). Automated translation has proven to be time and cost effective and is being applied in various projects at the author´s sponsoring company