A new Architecture for two-stage OTA with no-miller capacitor compensation

Author

Moallemi, S. ; Jannesari, Abumoslem

fYear

2012

fDate

3-4 Oct. 2012

Firstpage

180

Lastpage

183

Abstract

A new Architecture for two-stage Operational Transconductance Amplifier is presented. In this new structure the pole-zero cancellation technique is used to increase the amplifier band width. The proposed architecture uses a very simple circuit implementation scheme to create a feed-forward path in order to make a zero in voltage transfer function. The modularity of the proposed architecture also makes this scheme capable for use in multi-stage amplifier design. The DC-gain of 77dB, Unity-gain-bandwidth of 475 MHz is achieved while the OTA consumes only 5.1mW in standard CMOS 0.18μm technology with 1.8V power supply.

Keywords

CMOS integrated circuits; feedforward; integrated circuit design; operational amplifiers; poles and zeros; transfer functions; CMOS technology; OTA; bandwidth 475 MHz; feedforward path; gain 77 dB; multistage amplifier design; no-Miller capacitor compensation; pole-zero cancellation technique; power 5.1 mW; size 0.18 mum; two-stage operational transconductance amplifier; voltage 1.8 V; voltage transfer function; CMOS integrated circuits; CMOS technology; Capacitors; Frequency response; Poles and zeros; Transconductance; Transistors; Frequency Compensation; Operational Transconductance Amplifier (OTA); Slew Rate (SR); Unity Gain Band Width (UGBW);

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ICCAS), 2012 IEEE International Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4673-3117-3

Electronic_ISBN

978-1-4673-3118-0

Type

conf

DOI

10.1109/ICCircuitsAndSystems.2012.6408302

Filename

6408302