Title :
Low power tradeoffs in signal processing hardware primitives
Author :
Nagendra, Chetana ; Owens, Robert Michael ; Irwin, Mary Jane
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
In this paper, we present extensive simulation results for different types of parallel adders, which are the most frequently used primitives in digital signal processing. The adders studied include the linear time ripple carry and manchester carry chain adders, the logarithmic carry lookahead adders and its variations, the carry skip adder, and constant time signed-digit adders
Keywords :
adders; CMOS IC; carry skip adder; constant time signed-digit adders; digital signal processing; layout generation; linear time ripple carry adders; logarithmic carry lookahead adders; low power tradeoffs; manchester carry chain adders; parallel adders; signal processing hardware primitives; simulation; Adders; Computational modeling; Computer science; Computer simulation; Digital signal processing; Hardware; Microwave integrated circuits; Power engineering and energy; Signal design; Signal processing;
Conference_Titel :
VLSI Signal Processing, VII, 1994., [Workshop on]
Conference_Location :
La Jolla, CA
Print_ISBN :
0-7803-2123-5
DOI :
10.1109/VLSISP.1994.574752
