Title :
A method for generation of GSTE assertion graphs
Author_Institution :
Comput. Lab., Oxford Univ., UK
fDate :
30 Nov.-2 Dec. 2005
Abstract :
Generalized symbolic trajectory evaluation (GSTE) is a formal verification technique developed by Intel and used on next-generation microprocessor designs. One of its current drawbacks is that each property must be supplied in the form of a state-transition diagram known as an assertion graph. Assertion graphs are difficult to construct, to read and to reason about because they describe properties at a low level. In this paper, we propose a higher-level property language for GSTE in which we can specify properties as what we call assertion programs. We describe a way of applying weakest precondition calculations to these programs to generate assertion graphs. These can then be supplied to existing GSTE tools for verification.
Keywords :
automatic programming; formal verification; graphs; high level languages; software tools; GSTE; assertion graphs; assertion programs; formal verification; generalized symbolic trajectory evaluation; higher-level property language; next-generation microprocessor designs; state transition diagram; weakest precondition calculations; Automata; Automatic control; Buildings; Circuit simulation; Formal verification; Hardware; Laboratories; Large-scale systems; Microprocessors; Monitoring;
Conference_Titel :
High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International
Print_ISBN :
0-7803-9571-9
DOI :
10.1109/HLDVT.2005.1568831