A high-speed self-timed FIR processor implementation

Self-timed design can be used to avoid clock distribution problems in large high-speed VLSI systems. In this paper the self-timed design is applied to an FIR processor. Although DSP is not the most promising application field of self-timed design due to the fixed sampling rates, the benefits can be utilized in large DSP systems on silicon in specific application areas. Applications can be found, e.g., in image processing and telecommunication