• DocumentCode
    2911061
  • Title

    An optimum algorithm for compacting error traces for efficient functional debugging

  • Author

    Yen, Chia-Chih ; Jou, Jing-Yang

  • Author_Institution
    Dept. of Electron. Eng., National Chiao-Tung Univ., Hsinchu, Taiwan
  • fYear
    2005
  • fDate
    30 Nov.-2 Dec. 2005
  • Firstpage
    177
  • Lastpage
    183
  • Abstract
    Diagnosing counterexamples with error traces has acted as one of the most critical steps in functional verification. Unfortunately, error traces are normally very lengthy such that designers need to spend considerable effort to understand them. To alleviate designers´ burden for debugging, we present a SAT-based algorithm for reducing the lengths of error traces. The algorithm performs the paradigm of binary search algorithm to halve the search space recursively. Furthermore, it applies a theorem to guarantee to gain the shortest lengths for the error traces. Experimental results demonstrate that our approach greatly surpasses previous work and indeed has the optimum solutions.
  • Keywords
    Boolean functions; computability; errors; formal verification; program debugging; search problems; SAT-based algorithm; binary search algorithm; error traces; functional debugging; functional verification; optimum algorithm; Algorithm design and analysis; Collaboration; Compaction; Debugging; Hardware; Observability; Phase detection; Signal design; Testing; Writing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International
  • ISSN
    1552-6674
  • Print_ISBN
    0-7803-9571-9
  • Type

    conf

  • DOI
    10.1109/HLDVT.2005.1568834
  • Filename
    1568834