DocumentCode
2911086
Title
Increasing the deducibility in CNF instances for efficient SAT-based bounded model checking
Author
Vimjam, Vishnu C. ; Hsiao, Michael S.
Author_Institution
Dept. of Electr. & Comput. Eng.,, Virginia Tech, Blacksburg, VA, USA
fYear
2005
fDate
30 Nov.-2 Dec. 2005
Firstpage
184
Lastpage
191
Abstract
In this paper, we propose low-cost static deduction techniques by combining binary resolution and static logic implications to efficiently extract invariant relations from a gate-level netlist. We show that processing our techniques across the circuit nodes helps us to learn highly nontrivial relations. All the relations learned in a user-defined finite window are then quickly replicated over the entire bound for BMC. These powerful relations, when added as new constraint clauses to the original formula, help to significantly increase the deductive power for the SAT engine, thereby pruning a larger portion of the search space. Experimental results on ISCAS89 and ITC99 benchmarks show that more than an order of magnitude performance improvement can be obtained using the proposed learning techniques.
Keywords
Boolean functions; computability; formal verification; learning (artificial intelligence); logic design; search problems; CNF; SAT engine; binary resolution; bounded model checking; constraint clauses; gate-level netlist; learning techniques; performance improvement; static deduction; static logic; user-defined finite window; Binary decision diagrams; Computer bugs; Encoding; Engines; Hardware; Logic design; Monitoring; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International
ISSN
1552-6674
Print_ISBN
0-7803-9571-9
Type
conf
DOI
10.1109/HLDVT.2005.1568835
Filename
1568835
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