Title :
A 150 MHz wave-pipelined adaptive digital filter in 2 μm CMOS
Author :
Burleson, W.P. ; Lee, C.Y. ; Tan, E.J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
Adaptive filters have often been implemented using the conventional least mean squares (LMS) algorithm due to its inherent simplicity and robustness. However, its poor pipelinability greatly limits its use as a high-performance filter. In this paper, we present a wave-pipelined delayed LMS filter architecture using advanced retiming methods and algorithm modification. In addition to the arbitrarily high-sampling rate that is possible due to the delayed coefficient adaptation algorithm, we retime the signal-flow graph (SFG) of a proposed architecture in order to accommodate wave pipelining of the multiply-and-accumulate (MAC) block. The trade-off for reduced cycle time is an increase in the filter´s convergence time. The resulting systolic array implementation is highly pipelined for high-performance and is architecturally scalable because the sample rate is independent of the number of taps
Keywords :
adaptive filters; 150 MHz; 2 micron; CMOS DSP chip; LMS algorithm; algorithm modification; convergence time; delayed LMS filter architecture; delayed coefficient adaptation algorithm; least mean squares algorithm; multiply/accumulate block; retiming methods; signal-flow graph; systolic array implementation; wave-pipelined adaptive digital filter; Adaptive filters; Clocks; Degradation; Digital filters; Feedback; Least squares approximation; Pipeline processing; Propagation delay; Robustness; Systolic arrays;
Conference_Titel :
VLSI Signal Processing, VII, 1994., [Workshop on]
Conference_Location :
La Jolla, CA
Print_ISBN :
0-7803-2123-5
DOI :
10.1109/VLSISP.1994.574754
