Efficient power based Galois Field Arithmetic architectures

Galois Field has been used for numerous applications including error control coding and cryptography. The design of efficient multipliers, dividers and exponentiation circuits for Galois Field Arithmetic is needed for these applications. Recently, an approach based on pattern matching was developed which can yield a throughput of 1 result every clock cycle. We suggest an improvement to the existing design to reduce the hardware and critical path. This reduction in the critical path can lead to a higher speed or lower power implementation depending on the application. We also propose a new architecture to perform a general operation like ABⁿ+C. The new architecture is more efficient than the present schemes. The architecture presented has simple control, regular and local interconnection pattern and complete concurrency in operations and is therefore well suited for VLSI systems