Substrate Noise Isolation Experiments in a 0.18 μm 1P6M Triple-well CMOS process on a Lightly Doped Substrate

In order to help designers to protect analog-RF circuits against performance degradation due to substrate noise effects, a deep understanding of both noise propagation and impact mechanisms is mandatory. In this paper, coupling effects are investigated on different test structures implemented through a 0.18 μm 1P6M triple-well CMOS process. Results show the isolation performance dependence on substrate topologies, metal interconnections-to-substrate coupling and grounding of guarding structures. In particular, insertion of a P-Well Block region between the aggressor and the victim is proven to be a cheap strategy to improve isolation performance up to 20 dB, as compared with the Isolating Triple-Well structure with floating guard rings. Furthermore, analysis of guard rings grounding effects in triple-well topology shows that grounded N-Well/n+ guard ring improves isolation performance up to 8 dB at low frequency with respect to standard grounded p+ guard ring.