A 1 Gb/s deskew IC for RAMBUS automatic test application

Author

Hendarman, A. ; Choudhury, A. ; Yousefi, A. ; Armstrong, A.

Author_Institution

Vitesse Semicond. Corp., Camarillo, CA, USA

fYear

2000

fDate

5-8 Nov. 2000

Firstpage

89

Lastpage

92

Abstract

A deskew IC has been designed and fabricated using a 0.5-/spl mu/m GaAs E/D MESFET process. This IC is part of a five-chip chipset used in automatic test equipment for RAMBUS devices and currently shipping in a high-volume. The packaged IC consumes roughly 1/4 the board area and 1/2 the power of the bipolar alternative, allowing the entire high-speed section of a 32-DUT RAMBUS tester to fit in the test head. This paper describes the tester system architecture, circuit design techniques, and measured results of the deskew IC.

Keywords

MESFET integrated circuits; automatic test equipment; delay lock loops; integrated circuit testing; random-access storage; timing; 1 Gbit/s; E/D MESFET process; GaAs; RAMBUS automatic test; automatic test equipment; circuit design; coarse vernier; delay locked loop; deskew IC; fine vernier; five-chip chipset; memory tester; packaged IC; stability control block; tester system architecture; Application specific integrated circuits; Automatic test equipment; Automatic testing; Bipolar integrated circuits; Circuit testing; Gallium arsenide; Integrated circuit packaging; Integrated circuit testing; MESFET integrated circuits; Packaging machines;

fLanguage

English

Publisher

ieee

Conference_Titel

GaAs IC Symposium, 2000. 22nd Annual

Conference_Location

Seattle, WA, USA

ISSN

1064-7775

Print_ISBN

0-7803-5968-2

Type

conf

DOI

10.1109/GAAS.2000.906299

Filename

906299