DocumentCode :
2911987
Title :
A low noise on-chip matched MMIC LNA of 0.76 dB noise figure at 5 GHz for high speed wireless LAN applications
Author :
Choi, B.G. ; Lee, Y.S. ; Park, C.S. ; Yoon, K.S.
Author_Institution :
Sch. of Eng., Univ. of Inf. & Commun., Taejon, South Korea
fYear :
2000
fDate :
5-8 Nov. 2000
Firstpage :
143
Lastpage :
146
Abstract :
A 2-stage PHEMT MMIC low noise amplifier of very low noise figure as low as 0.76 dB and gain over 16 dB at 5 GHz has been implemented using a minimum input matching network. The input network of the first stage was designed employing a small inductance of 0.89 nH to the gate of PHEMT series feedback amplifier whose gate width and series inductance were optimized for a simultaneous noise and VSWR match. We believe that the noise figure of 0.76 dB with 3 V operation in this work is the best result ever reported to date from MMIC LNAs around this frequency range, and is attributed to the minimized input matching network to the low noise PHEMT.
Keywords :
HEMT integrated circuits; MMIC amplifiers; feedback amplifiers; integrated circuit noise; wireless LAN; 0.76 dB; 16 dB; 3 V; 5 GHz; PHEMT MMIC low noise amplifier; VSWR; gain; high-speed wireless LAN; inductance; noise figure; on-chip input matching network; series feedback amplifier; Design optimization; Feedback amplifiers; Frequency; Gain; Impedance matching; Inductance; Low-noise amplifiers; MMICs; Noise figure; PHEMTs;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
GaAs IC Symposium, 2000. 22nd Annual
Conference_Location :
Seattle, WA, USA
ISSN :
1064-7775
Print_ISBN :
0-7803-5968-2
Type :
conf
DOI :
10.1109/GAAS.2000.906310
Filename :
906310
Link To Document :
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