DocumentCode :
2912066
Title :
Correlation of no trouble found errors to Negative Bias Temperature Instability
Author :
LiVolsi, Robert ; McCormick, Kevin ; Torres, Myra ; Velamala, Jyothi ; Zheng, Rui ; Cao, Yu
Author_Institution :
Impact Technol., LLC, Rochester, NY, USA
fYear :
2011
fDate :
5-12 March 2011
Firstpage :
1
Lastpage :
8
Abstract :
No Trouble Found (NTF) and Cannot Duplicate (CND) errors on modern digital electronics are increasingly prevalent and occur at a rate of 50-60% using conventional bench top diagnostics. This work correlates NTF diagnostic errors to Negative Bias Temperature Instability (NBTI), a prominent failure degradation mode and self annealing mechanism in sub-100 nm CMOS technology. NBTI degradation is duplicated in laboratory experiments on 90 nm MPC7448 Freescale Microprocessors. Accelerated aging via in situ thermal and voltage cycling is conducted while benchmark scripts are running on the MPC7448. Faults observed include premature program termination, corruption of system services, L1 and L2 cache errors as reported by the kernel, and total system failure. After 8 hours of rest, the system boots up normally with no indication of system degradation. Final system failure is observed after several faults. Conventional Built-In Test (BIT) fails to detect these faults upon reboot of the system. Various control tests and test profiles are used to accelerate NBTI degradation on the microprocessor samples. The challenge of faulty behavior is distinguishing between health and degradation leading to failure. Analysis techniques are used to show separation between healthy and degraded data, and independent NBTI research at Arizona State University is used to correlate NBTI behavior to NTF diagnostic errors.
Keywords :
CMOS digital integrated circuits; annealing; failure analysis; integrated circuit reliability; integrated circuit testing; microprocessor chips; thermal stability; CMOS technology; L1 cache error; L2 cache error; MPC7448 freescale microprocessors; NTF diagnostic errors; conventional built-in test; failure degradation mode; microprocessor samples; negative bias temperature instability; no trouble found errors; self-annealing mechanism; size 90 nm; system reboot; total system failure; voltage cycling; Aging; Annealing; CMOS integrated circuits; Degradation; Process control; Stress; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Aerospace Conference, 2011 IEEE
Conference_Location :
Big Sky, MT
ISSN :
1095-323X
Print_ISBN :
978-1-4244-7350-2
Type :
conf
DOI :
10.1109/AERO.2011.5747585
Filename :
5747585
Link To Document :
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