Non-linearity in high gain CMOS buffer amplifiers for CCD processor applications

Author

Laquerre, Pierre ; Bernal, Olivier ; Lescure, Marc

Author_Institution

ENSEEIHT, Toulouse

fYear

2007

fDate

1-3 May 2007

Firstpage

1

Lastpage

6

Abstract

The linearity of CMOS buffer amplifiers is discussed. It is shown that enhancing the amplifier gain to reduce non-linearity presents limitations due to small signal gain mismatches between the two amplifier inputs. An amplifier structure and associated design precautions are proposed to overcome these limitations to some extent. As a result, a fully differential buffer used in a 12 bit 10 MSamples/s video chain has been successfully designed to achieve 16 bits linearity in a low-voltage CMOS 0.35 mum process.

Keywords

CCD image sensors; buffer circuits; differential amplifiers; low-power electronics; CCD processor; amplifier gain; high gain CMOS buffer amplifier nonlinearity; low-voltage CMOS process; signal gain mismatches; size 0.35 mum; video chain; word length 12 bit; word length 16 bit; CMOS process; CMOS technology; Charge coupled devices; Circuits; Instrumentation and measurement; Linearity; Operational amplifiers; Steady-state; Transfer functions; Video signal processing; CCD; CMFB loop; Differential amplifier; Linearity; Low-voltage CMOS; gain mismatch;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference Proceedings, 2007. IMTC 2007. IEEE

Conference_Location

Warsaw

ISSN

1091-5281

Print_ISBN

1-4244-0588-2

Type

conf

DOI

10.1109/IMTC.2007.379450

Filename

4258309