Architecture and VLSI implementation of a RISC core for a monolithic video signal processor

Author

Herrmann, Klaus ; Seifert, Martin ; Gaedke, Klaus ; Jeschke, Hartwig ; Pirsch, Peter

Author_Institution

Lab. fur Informationstechnol., Hannover Univ., Germany

fYear

1994

fDate

1994

Firstpage

368

Lastpage

377

Abstract

For a monolithic video signal processor a special RISC processor core has been developed. In order to achieve an efficient implementation of hybrid video coding algorithms the applied Harvard architecture with 16 bit data path is adapted to tasks like quantization, variable length coding and run length coding. The RISC processor´s die size is 68.79 mm ² fabricated in a 0.8 μm CMOS technology. 4 kByte of program RAM and 512 Bytes of Data Memory are implemented on chip. The operating frequency is 66 MHz

Keywords

VLSI; 0.8 micron; 16 bit; 4 kByte; 512 Byte; 66 MHz; 68 mm; 79 mm; CMOS technology; Harvard architecture; RISC core; VLSI; data memory; data path; hybrid video coding algorithms; monolithic video signal processor; program RAM; quantization; run length coding; variable length coding; CMOS process; CMOS technology; Quantization; Random access memory; Read-write memory; Reduced instruction set computing; Signal processing; Signal processing algorithms; Very large scale integration; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Signal Processing, VII, 1994., [Workshop on]

Conference_Location

La Jolla, CA

Print_ISBN

0-7803-2123-5

Type

conf

DOI

10.1109/VLSISP.1994.574761

Filename

574761