DocumentCode
2912873
Title
Thermal characterization of vias using compact models
Author
Pinjala, D. ; Iyer, Mahadevan K. ; Guan, Chow Seng ; Rasiah, Ignatius J.
Author_Institution
Inst. of Microelectron., Singapore
fYear
2000
fDate
2000
Firstpage
144
Lastpage
147
Abstract
Thermal vias and balls are key elements in plastic ball grid array (PBGA) package thermal design as they enhance the package performance. Simulation is a versatile design optimization tool for characterizing the thermal vias and balls. However, the finer geometric details of the vias require excessive memory and modeling and simulation time. Different modeling concepts are being tried in the industry to include finer geometries in the package. This paper shows a methodology of developing compact thermal via models and validating the same with detailed models. The accuracy of compact thermal via models with respect to the detailed models has been determined using PBGA 352 as the test vehicle. It is found that the accuracy is within 3%. The simulation models of PBGA 352 have been validated by measurements and found that the accuracy of model is within 10%. Two and four layer PBGA 352s with different via configurations have been characterized with compact thermal via models, and design guidelines for PBGA 352 packages have been obtained
Keywords
ball grid arrays; circuit CAD; circuit optimisation; circuit simulation; cooling; integrated circuit design; integrated circuit measurement; integrated circuit modelling; integrated circuit packaging; plastic packaging; thermal analysis; thermal conductivity; thermal management (packaging); PBGA 352 test vehicle; PBGA measurements; PBGA package thermal design; compact models; design guidelines; design optimization tool; memory requirements; model validation; modeling; multilayer PBGA; package geometries; package performance; plastic ball grid array package thermal design; simulation; simulation models; simulation time; thermal balls; thermal characterization; thermal via models; thermal vias; via configurations; via geometric details; vias; Copper; Dielectric substrates; Electronic packaging thermal management; Electronics packaging; Guidelines; Plastic packaging; Solid modeling; Testing; Thermal conductivity; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 2000. (EPTC 2000). Proceedings of 3rd
Print_ISBN
0-7803-6644-1
Type
conf
DOI
10.1109/EPTC.2000.906363
Filename
906363
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