Title :
A 100 MHz pipelined RLS adaptive filter
Author :
Raghunath, Kalavai J. ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
Previously, a new pipelinable PSTAR-RLS algorithm was developed. It was shown to be an effective alternative to the QRD-RLS algorithm when high-speeds are required. Using a folding technique, a 4-tap PSTAR-RLS algorithm was implemented on a single VLSI chip. All the operations in the chip are bit-level pipelined. With a 1.2 μ CMOS technology this chip is expected to run at 100 MHz. Redundant number system based arithmetic operators were used for performance advantage. Apart from a wafer scale implementation, this is the first ever single chip ASIC implementation of a RLS adaptive filter
Keywords :
CMOS digital integrated circuits; VLSI; adaptive filters; application specific integrated circuits; digital filters; least squares approximations; parallel algorithms; parallel architectures; pipeline arithmetic; recursive filters; redundant number systems; 1.2 micron; 100 MHz; 100 MHz pipelined RLS adaptive filter; 4-tap PSTAR-RLS algorithm; ASIC implementation; CMOS technology; RLS adaptive filter; VLSI chip; bit-level pipeline; folding technique; performance; pipelinable PSTAR-RLS algorithm; redundant number system based arithmetic operators; wafer scale implementation; Adaptive equalizers; Adaptive filters; Application specific integrated circuits; Arithmetic; CMOS technology; Filtering algorithms; Least squares approximation; Least squares methods; Resonance light scattering; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1995. ICASSP-95., 1995 International Conference on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-2431-5
DOI :
10.1109/ICASSP.1995.479562
