A novel memory controller for an ATM switch

Author

Keller, Hj. ; Schürch, H. ; Rao, S.

Author_Institution

Ascom Tech Tricom, Bern, Switzerland

fYear

1990

fDate

5-8 Mar 1990

Firstpage

103

Lastpage

114

Abstract

The authors discuss some general approaches to ATM (asynchronous transfer mode) switching architectures, namely, common memory switches, Banyan networks, switch matrices, and bus-based time switches from a traffic behavior and implementation viewpoint. They focus on a novel controller hardware for the common memory type, which implements FIFO (first-in first-out) mechanisms as linked lists in hardware. The architecture for a 8×8 switch block implementation is elaborated in CMOS technology

Keywords

CMOS integrated circuits; electronic switching systems; integrated circuit technology; telecommunications computer control; time division multiplexing; ATM switch; Banyan networks; CMOS technology; FIFO; asynchronous transfer mode; broadband communications; bus-based time switches; common memory switches; first-in first-out; memory controller; switch matrices; switch technology; switching architectures; Asynchronous transfer mode; Bandwidth; Buffer overflow; Communication switching; Communication system control; Hardware; Switches; Switching circuits; Telecommunication traffic; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital Communications, 1990. Electronic Circuits and Systems for Communications. Proceedings, 1990 International Zurich Seminar on

Conference_Location

Zurich

Type

conf

DOI

10.1109/DIGCOM.1990.129364

Filename

129364