Cell alignment in ATM systems via header error check: performance evaluation and hardware considerations

Cell synchronization for an asynchronous transfer mode (ATM) system via header error check is discussed, and a possible hardware implementation is given. For a performance evaluation the essential parameters are average cell loss and mean block length of the consecutively lost cells. For these parameters, formulae, or at least lower and upper bounds in closed form, are derived. The derivation is based on a formal description of the system with Markov models. It is shown that satisfactory performance is achieved at the expense of an elaborate hardware implementation. The characteristic of this hardware implementation is the evaluation of codewords with a circuit which is clocked by the bit clock of the incoming bit stream. Thus, there is no need for a very high speed decoder design since the decoder can be implemented in the same technology as the surrounding circuits