Title :
Applications of newly developed positive photosensitive block co-polyimides to CSPs
Author :
Matsumoto, Shunichi ; Jin, Xing Zhou ; Fukushima, Takahumi ; Miyamura, Masataka ; Itatani, Hirosi
Author_Institution :
P I R&D Co. Ltd, Yokohama, Japan
Abstract :
Meeting the challenging market-defined needs of CSPs requires a new substrate technology to provide higher I/O densities, higher performance, thinner and lighter packaging structures. In this paper, applications to CSP interposer (CSP-IP) processes of newly developed positive photosensitive block co-polyimides (PPI) are discussed. Block co-polyimides are prepared in organic polar solvents by a sequential addition co-polymerization process in the presence of a binary catalyst. PPI polymer solutions are derived from block co-polyimides including photo-sensitizers. Advantages of these PPIs include: (1) no imidization process needs at high temperature; (2) PPIs with strong adhesion to Cu, Al and Si wafers; (3) thinner polyimide films with high durability; (4) positive photo-patterns with high resolution; (5) PPIs with high Tg . In CSP-IP packaging processes using PPI, PPI´s UV resolution workability gives highly uniform 20 μm diameter via holes and highly uniform solder bumps attached to the polyimide layers. As PPI requires no imidization process after drying and curing, the heat requirements of CSP-IP processes are under 200°C, which enables additional layers of lead I/O patterning between solder bumps without any solder bump deformations, giving higher I/O densities and size reduction to the new CSP-IP. PPI´s pin-holeless performance using black masks in the processes keeps CSP-IP production cost very low, and it is possible to coat PPI polymer solutions directly on Si wafers to produce a wafer CSP with high production yield at low cost. Thinner layered CSP-IP packages by PPI could be applied to 3D-stacked CSP features
Keywords :
adhesion; chip scale packaging; drying; encapsulation; heat treatment; integrated circuit interconnections; integrated circuit yield; plastic packaging; polymer blends; polymer films; soldering; ultraviolet lithography; 20 micron; 200 C; 3D-stacked CSP features; Al; Al adhesion; CSP interposer processes; CSP-IP packaging processes; CSP-IP process heat requirements; CSP-IP production cost; CSPs; Cu; Cu adhesion; I/O density; PPI polymer solutions; Si; Si wafer adhesion; Si wafers; UV resolution workability; binary catalyst; black masks; block co-polyimides; curing; drying; durability; glass transition; imidization process; layered CSP-IP packages; lead I/O patterning layers; organic polar solvents; packaging structures; performance; photo-pattern resolution; photo-sensitizers; pin-holeless performance; polyimide film thickness; polyimide layers; positive photo-patterns; positive photosensitive block co-polyimides; production yield; sequential addition co-polymerization process; size reduction; solder bump deformation; solder bumps; substrate technology; uniform solder bumps; via holes; wafer CSP; Adhesives; Chip scale packaging; Costs; Polyimides; Polymers; Production; Semiconductor films; Solvents; Temperature; Workability;
Conference_Titel :
Electronics Packaging Technology Conference, 2000. (EPTC 2000). Proceedings of 3rd
Print_ISBN :
0-7803-6644-1
DOI :
10.1109/EPTC.2000.906402