DocumentCode :
2914436
Title :
Optimal table lookup schemes for VLSI implementation of input/output conversions and other residue number operations
Author :
Parhami, B. ; Hung, C.Y.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear :
1994
fDate :
1994
Firstpage :
470
Lastpage :
481
Abstract :
Residue number representation has become a viable alternative for fast, area-efficient VLSI realization of high-performance signal processing hardware. Wider applicability and improved cost/performance of residue-based VLSI implementations of signal processing algorithms are critically dependent on efficient realization of I/O data conversions and several other support functions that are treated in this paper. Alternate table-lookup schemes for conversion of binary to residue numbers, and vice versa, are presented. Input widths of lookup tables can be changed freely through a repartitioning scheme to provide tradeoffs between table size (area) and computation speed. Improved variants of VLSI-based pipelined binary-to-residue converters are derived along with balanced, highly regular, pipelined architectures for residue-to-binary conversion in VLSI. The input repartitioning method is shown to be applicable to other important residue number system operations, including sign detection, mixed-radix conversion, and base extension
Keywords :
table lookup; I/O data conversions; area-efficient VLSI realization; base extension; computation speed; high-performance signal processing hardware; input repartitioning method; input/output conversions; mixed-radix conversion; pipelined architectures; pipelined binary-to-residue converters; repartitioning scheme; residue number operations; residue-based VLSI implementations; residue-to-binary conversion; sign detection; support functions; table lookup schemes; table size; Arithmetic; Computer architecture; Cost function; Data conversion; Hardware; Read only memory; Signal design; Signal processing algorithms; Table lookup; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Signal Processing, VII, 1994., [Workshop on]
Conference_Location :
La Jolla, CA
Print_ISBN :
0-7803-2123-5
Type :
conf
DOI :
10.1109/VLSISP.1994.574771
Filename :
574771
Link To Document :
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