A High Spurious-Free Dynamic Range 4-bit ADC with Nyquist Signal Bandwidth for Wideband Communications

Author

Wang, Mingzhen ; Chen, Chien-In Henry

Author_Institution

Wright State Univ., Dayton

fYear

2007

fDate

1-3 May 2007

Firstpage

1

Lastpage

5

Abstract

A 2.5-GS/s 4-bit flash ADC with high SFDR for wideband communication systems is designed using a standard 130 nanometer digital CMOS process. A new clocked digital comparator with dynamic offset suppression is proposed to improve ADC dynamic performance. In our simulation, SFDR of this 4-bit ADC achieve 36.88 dB at 9.766 MHz input signal. Near Nyquist frequency input signals, SFDR maintains above 19.81 dB, at up to 1.248 GHz. This ADC has a two-and-half clock cycle latency and a low input capacitance of 300 fF. The power consumption of ADC is 1.35 mW with 1.2-V voltage supply at a 2.5 GHz conversion rate.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; broadband networks; comparators (circuits); power consumption; Nyquist signal bandwidth; analog-digital conversion; clocked digital comparator; digital CMOS process; dynamic offset suppression; flash ADC; frequency 2.5 GHz; power 1.35 mW; power consumption; size 130 nm; voltage 1.2 V; wideband communications; word length 4 bit; Bandwidth; CMOS process; Capacitance; Clocks; Communication standards; Delay; Dynamic range; Energy consumption; Frequency; Wideband; Low-power; analog-to-digital converter (ADC); comparator; encoder; flash ADC; low-voltage; pipelined ADC; thermometer-to-binary;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference Proceedings, 2007. IMTC 2007. IEEE

Conference_Location

Warsaw

ISSN

1091-5281

Print_ISBN

1-4244-0588-2

Type

conf

DOI

10.1109/IMTC.2007.379376

Filename

4258443