A High Spurious-Free Dynamic Range 4-bit ADC with Nyquist Signal Bandwidth for Wideband Communications

A 2.5-GS/s 4-bit flash ADC with high SFDR for wideband communication systems is designed using a standard 130 nanometer digital CMOS process. A new clocked digital comparator with dynamic offset suppression is proposed to improve ADC dynamic performance. In our simulation, SFDR of this 4-bit ADC achieve 36.88 dB at 9.766 MHz input signal. Near Nyquist frequency input signals, SFDR maintains above 19.81 dB, at up to 1.248 GHz. This ADC has a two-and-half clock cycle latency and a low input capacitance of 300 fF. The power consumption of ADC is 1.35 mW with 1.2-V voltage supply at a 2.5 GHz conversion rate.