DocumentCode :
2915967
Title :
Use of PLDs to illustrate fundamental concepts in switching and logic
Author :
Grover, Jim ; Ugweje, Okechukwu
Author_Institution :
Dept. of Electr. & Comput. Eng., Akron Univ., OH, USA
Volume :
3
fYear :
2002
fDate :
6-9 Nov. 2002
Abstract :
This paper discusses the application of programmable logic devices (PLDs) to enhance the understanding of digital design at the University of Akron. The Switching and Logic course has often been taught as a classical engineering class where students have little or no hands-on experience, and sometimes have difficulty in understanding the basic concept. With the availability of lower-cost, digital and logic components, and test equipment, this is changing. For freshman and sophomore engineering students taking an introduction to digital design, one must make sure that error in implementation such as wiring errors do not prevent the concept of design from getting through. To ease implementation problems at the university, programmable logic devices in the form of ICT PEELsTM and PEELTM arrays are used with motherboard and daughter boards. The configuration tools are easy to use and available at no cost to the students for home use. Two and multilevel implementation are investigated for both combinational and sequential networks. The motherboard, daughter board combination was locally developed allowing their resources to closely track the accompanying laboratory exercises. By reducing wiring to a minimum laboratory, exercises can range from analysis to design and be accomplished in the allotted three-hour period. The overall effectiveness of this instructional model has been positive, and this continues to be used and expanded.
Keywords :
computer aided instruction; electronic engineering education; logic design; programmable logic arrays; student experiments; switching; ICT PEELS; PEEL arrays; Switching and Logic course; University of Akron; combinational networks; configuration tools; daughter boards; digital design; freshman engineering students; laboratory exercises; motherboard; multilevel implementation; programmable logic devices; sequential networks; sophomore engineering students; two level implementation; wiring errors; Circuit simulation; Costs; Field programmable gate arrays; Laboratories; Logic circuits; Logic devices; Logic programming; Programmable logic arrays; Programmable logic devices; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Frontiers in Education, 2002. FIE 2002. 32nd Annual
ISSN :
0190-5848
Print_ISBN :
0-7803-7444-4
Type :
conf
DOI :
10.1109/FIE.2002.1158739
Filename :
1158739
Link To Document :
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