Title :
A pipelined bilinear interpolation for real time video image expansion
Author :
Uthaichana, Patheera ; Leelarasmee, Ekachai
Author_Institution :
Dept. of Electr. Eng., Chulalongkorn Univ., Bangkok, Thailand
Abstract :
A hardware for expanding an image window of a TV screen in real time is proposed. It uses bilinear interpolation to enlarge a window of size at least 128×128 pixels by 4 times. It consists of a video decoder/encoder for converting a composite video signal into a 27 MByte/sec ITU-R BT.656 standard digital format and vice versa, three memory chips for storing partially or fully expanded images and an FPGA programmed as an expansion controller. The FPGA implements the bilinear interpolation of the digitized image by splitting into horizontal and vertical expansions that can be pipelinely executed within a delay of two video frame or 80 msec. Using an infrared remote controller, a deaf person can locate the sign language window and turn on its expansion to suit his viewing need.
Keywords :
digital video broadcasting; field programmable gate arrays; interpolation; pipeline processing; telecontrol; video coding; FPGA programming; TV screen; deaf person; digital video processing; infrared remote controller; memory chip; pipelined bilinear interpolation; video decoder-encoder; video image expansion; Interpolation;
Conference_Titel :
TENCON 2004. 2004 IEEE Region 10 Conference
Print_ISBN :
0-7803-8560-8
DOI :
10.1109/TENCON.2004.1414908