DocumentCode
2916348
Title
A floating-gate track-and-hold circuit with robustness to component mismatches
Author
Worapishet, Apisak ; Moolpho, Kornnika ; Ngarmnil, Jitkasame
Author_Institution
Mahanakorn Microelectron. Res. Centre, Mahanakorn Univ. of Technol., Bangkok, Thailand
Volume
D
fYear
2004
fDate
21-24 Nov. 2004
Firstpage
286
Abstract
A track-and-hold (T/H) circuit using the floating-gate (FG) technique is introduced based upon a pair of complementary FGMOS transistors. Its main features include low complexity, low operating supply voltage and gain insensitivity to device mismatches. Emphasis is given on the circuit operation. Functional verification is provided through simulated performances of a single T/H cell.
Keywords
CMOS analogue integrated circuits; sample and hold circuits; device mismatches; floating-gate technique; robustness; track and hold circuit; Capacitance; Capacitors; Circuit simulation; Clocks; Coupling circuits; Inverters; Robustness; Sampling methods; Signal processing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2004. 2004 IEEE Region 10 Conference
Print_ISBN
0-7803-8560-8
Type
conf
DOI
10.1109/TENCON.2004.1414925
Filename
1414925
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