Title :
High performance multilayer routing for VLSI circuit synthesis
Author :
Bhowal, Sangramjit ; Pal, Rajat K.
Author_Institution :
Dept. of Comput. Sci. & Eng., Netaji Subhas Eng. Coll., Kolkata, India
Abstract :
This paper presents algorithms for interconnecting the terminals in a channel using a minimum amount of crosstalk in minimum area. Algorithms are developed for grid-based routing models in two-layer (VH), three-layer (VHV and HVH), and four-layer (VHVH) channels. Our channel routers use only no-dogleg wires and resolve vertical constraints efficiently. The routers are executed for several well-known benchmark channel instances and results obtained are highly encouraging.
Keywords :
VLSI; integrated circuit design; integrated circuit interconnections; network routing; VLSI circuit synthesis; VLSI design; crosstalk minimization; grid-based routing model; multilayer channel routing; no-dogleg wire; terminal interconnection; Circuit synthesis; Computer science; Coupling circuits; Crosstalk; Educational institutions; Frequency; Integrated circuit interconnections; Routing; Very large scale integration; Wire;
Conference_Titel :
TENCON 2004. 2004 IEEE Region 10 Conference
Print_ISBN :
0-7803-8560-8
DOI :
10.1109/TENCON.2004.1414936
