Exploiting SPM-aware Scheduling on EPIC architectures for high-performance real-time systems

Author

Yu Liu ; Wei Zhang

Author_Institution

Dept. of ECE, Virginia Commonwealth Univ., Richmond, VA, USA

fYear

2012

fDate

10-12 Sept. 2012

Firstpage

1

Lastpage

2

Abstract

In contemporary computer architectures, the Explicitly Parallel Instruction Computing Architectures (EPIC) permits microprocessors to implement Instruction Level Parallelism (ILP) by using the compiler, rather than complex on-die circuitry to control parallel instruction execution like the superscalar architecture. Based on the EPIC, this paper proposes a time predictable two-level scratchpad based memory architecture, and a Scratchpad-aware Scheduling method to improve the performance by optimizing the Load-To-Use Distance.

Keywords

memory architecture; microprocessor chips; parallel architectures; program compilers; real-time systems; scheduling; EPIC architectures; ILP; SPM-aware scheduling; compiler; complex on-die circuitry; computer architectures; explicitly parallel instruction computing architectures; high-performance real-time systems; instruction level parallelism; load-to-use distance; microprocessors; scratchpad-aware scheduling method; superscalar architecture; time predictable two-level scratchpad based memory architecture; Benchmark testing; Memory architecture; Microprocessors; Processor scheduling; Program processors; Real-time systems; Real-Time Systems; SPMs;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Extreme Computing (HPEC), 2012 IEEE Conference on

Conference_Location

Waltham, MA

Print_ISBN

978-1-4673-1577-7

Type

conf

DOI

10.1109/HPEC.2012.6408658

Filename

6408658