Title :
Logic synthesis and technology mapping of MUX-based FPGAs for high performance and low power
Author :
Marik, Maitrali ; Pal, Ajit
Author_Institution :
IBM Global Services, India
Abstract :
The problem of logic synthesis and technology mapping for Actel-1 MUX-based FPGAs in the context of low power applications has been addressed in this paper. Decomposed BDD representation, which helps to deal with large Boolean functions, has been used in the technology independent as well as technology mapping phases of the proposed synthesis approach. To minimize area, delay and power dissipation of the realized circuits, several novel optimization techniques have been adopted in both the phases. Efficacy of the proposed approach has been demonstrated with the help of experimental results on a large number of ISCAS benchmark circuits.
Keywords :
benchmark testing; binary decision diagrams; field programmable gate arrays; logic testing; low-power electronics; multiplexing; optimisation; Actel-1 MUX-based FPGA; Boolean function; ISCAS benchmark circuit; binary decision diagram; decomposed BDD representation; delay; logic synthesis; low power application; optimization technique; power dissipation; technology mapping; Binary decision diagrams; Boolean functions; Capacitance; Circuit synthesis; Context-aware services; Delay; Field programmable gate arrays; Logic circuits; Power dissipation; Voltage;
Conference_Titel :
TENCON 2004. 2004 IEEE Region 10 Conference
Print_ISBN :
0-7803-8560-8
DOI :
10.1109/TENCON.2004.1414959
