• DocumentCode
    2917170
  • Title

    A processor scheduling design for gateways in heterogeneous data networks

  • Author

    Yue, On-Ching

  • Author_Institution
    AT&T Bell Labs., Holmdel, NJ, USA
  • fYear
    1990
  • fDate
    5-8 Mar 1990
  • Firstpage
    373
  • Lastpage
    386
  • Abstract
    The performance of the limited-k policy for processor scheduling in gateways is analyzed. For bilateral gateways handling inbound and outbound traffic between a subnetwork and the backbone, this policy limits the number of messages served by the processor in one direction before switching to the other direction. The limited-k policy provides two tunable parameters for controlling the message delay, even under overload conditions in one direction. The applicable bounds on delays are discussed, and a throughput analysis is given. Simulation results are presented which provide guidance on how the parameters should be chosen based on relative traffic intensities. Also included are performance bounds for fixed parameter settings but arbitrary traffic intensities including overload in one direction
  • Keywords
    computer networks; data communication systems; delays; queueing theory; scheduling; LAN; MAN; WAN; bilateral gateways; gateways; heterogeneous data networks; limited-k policy; message delay; overload conditions; performance bounds; processor scheduling design; queueing theory; subnetwork; throughput analysis; traffic intensities; tunable parameters; Data communication; Delay; Intelligent networks; Local area networks; Optical fibers; Physical layer; Process design; Processor scheduling; Protocols; Wide area networks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital Communications, 1990. Electronic Circuits and Systems for Communications. Proceedings, 1990 International Zurich Seminar on
  • Conference_Location
    Zurich
  • Type

    conf

  • DOI
    10.1109/DIGCOM.1990.129385
  • Filename
    129385