Area efficient fast Huffman decoder for multimedia applications

Proposes an area-efficient VLSI architecture for fast Huffman decoder which can support HDTV rates. Huffman coding, which is known as optimal variable length coding, has been widely used to reduce storage and communication channel bandwidth, and several emerging image compression standards such as JPEG, MPEG, CCITT H.261 require to perform Huffman coding in real-time with high throughput. However, most known designs are not suitable for real-time operation or for implementation, especially in HDTV, since these require large amount of VLSI area or a large number of processing elements (PEs) for high performance. The proposed VLSI architecture for the Huffman decoder requires fewer comparators and smaller size of data rotator to simulate the Barrel shifter. It can decode up to 17 bits per cycle and employs a 40 MHz clock which can support HDTV rates. Thus, it can decode Huffman coded sequences up to 680 Mbits/s at peak. Compared with the parallel implementation in Mukherjee et al. (1991) which requires upto 1460 PEs and has 10 Mbps of throughput, the proposed architecture is a single PE design with competitive processing power. It requires 25% of the area of the known single PE design in Lei and Sun (1991)