A programmable motion estimation processor for full search block matching

Author

Pirson, Alain ; Yassa, Fathy ; Paul, Philippe ; Canfield, Barth ; Rominger, Friedrich ; Graf, Andreas ; Teichner, Detlef

Author_Institution

Thomson Consumer Electron. Components, Meylan, France

Volume

5

fYear

1995

fDate

9-12 May 1995

Firstpage

3283

Abstract

Describes a programmable motion estimation processor applying a block matching technique on large search windows. Developed in the context of an MPEG-2 video encoder, its use can be extended to any application where fast motion estimation is required. Its high performance (17 Gops peak) and its ability to work in parallel make it ideal for real time applications like video compression. The block matching processor (BMP) consists of a CPU associated with several specific units including a fast motion estimator, a DRAM interface, IO ports and some on-chip memory. This approach allies the flexibility of a CPU to the efficiency of dedicated hardware. A DRAM controller minimizes the impact of data transfer on the computing power

Keywords

VLSI; data compression; digital signal processing chips; image matching; motion estimation; search problems; systolic arrays; telecommunication standards; video coding; DRAM controller; DRAM interface; IO ports; MPEG-2 video encoder; block matching processor; computing power; data transfer; full search block matching; large search windows; on-chip memory; programmable motion estimation processor; real time applications; video compression; Consumer electronics; Hardware; ISO standards; Motion estimation; Random access memory; Standards organizations; Transform coding; Very large scale integration; Video compression; Video sequences;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1995. ICASSP-95., 1995 International Conference on

Conference_Location

Detroit, MI

ISSN

1520-6149

Print_ISBN

0-7803-2431-5

Type

conf

DOI

10.1109/ICASSP.1995.479587

Filename

479587