High voltage NMOS double hump prevention by using baseline CMOS p-well implant

The high voltage device can be embedded into conventional shallow trench isolation (STI) logic process. Basically, SVX (Smart Voltage Extension) technique was applied in order to integrate 32 V high voltage LDMOS into a standard 0.18 micron low voltage CMOS technology without any process change. However, a double hump issue was being observed in high voltage LDNMOS. The double hump phenomenon is mainly occurs due to lower threshold voltage of transistor corner that will lead to high sub-threshold leakage. This paper presents a solution by applying boron implant in HV LDNMOS to suppress the double hump issue. The retrograde baseline CMOS p-well implant is used for this purpose to avoid an additional mask and process step.