DocumentCode :
2918652
Title :
Using a Balanced Quad List Quad Tree to Speed Up a Hierarchical VLSI Compaction Scheme
Author :
Hsiao, Pei-Yung ; Jang, Lih-Der
Author_Institution :
National Chiao Tung University
fYear :
1992
fDate :
4-7 Jan 1992
Firstpage :
370
Lastpage :
371
Keywords :
Compaction; Data structures; Design automation; High level synthesis; Information science; Layout; Shape; Tree data structures; Tree graphs; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1992. Proceedings., The Fifth International Conference on
ISSN :
1063-9667
Print_ISBN :
0-8186-2465-5
Type :
conf
DOI :
10.1109/ICVD.1992.658091
Filename :
658091
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2918652
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