Title :
DEFLAN- A delay estimator for floorplanner
Author_Institution :
Application Specific Products Group, Texas Instruments
Keywords :
Added delay; Capacitance; Chip scale packaging; Cost function; Delay effects; Delay estimation; Design automation; Routing; Timing; Upper bound;
Conference_Titel :
VLSI Design, 1992. Proceedings., The Fifth International Conference on
Print_ISBN :
0-8186-2465-5
DOI :
10.1109/ICVD.1992.658092
