Title :
Design of A 100MHz – 1.66GHz, 0.13µm CMOS phase locked loop
Author :
Ayat, Mehdi ; Babaei, Behnam ; Atani, Reza Ebrahimi ; Mirzakuchaki, Sattar ; Zamanlooy, Babak
Author_Institution :
Dept. of Electr. Eng., Iran Univ. of Sci. & Technol., Tehran, Iran
Abstract :
A fully integrated charge-pump phase-locked loop (PLL) is described. The PLL is designed and simulated in a 0.13 CMOS technology. The PLL lock range is from 100MHz to 1.66GHz.
Keywords :
CMOS integrated circuits; phase locked loops; CMOS phase locked loop; PLL; frequency 100 MHz to 1.66 GHz; fully integrated charge-pump phase-locked loop; size 0.13 mum; CMOS technology; Charge pumps; Clocks; Filters; Impedance matching; Integrated circuit technology; Phase detection; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Electronic Devices, Systems and Applications (ICEDSA), 2010 Intl Conf on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-6629-0
DOI :
10.1109/ICEDSA.2010.5503082
