Title :
An all-digital clock and data recovery circuit for low-to-moderate data rate applications
Author :
Tall, N. ; Dehaese, N. ; Bourdel, S. ; Bonat, B.
Author_Institution :
IM2NP, Aix-Marseille Univ., Marseille, France
Abstract :
This paper deals with a digital clock and data recovery (CDR) circuit for low-to-moderate data rate applications. The design is based on the analogy between an analog charge-pump based phase-locked loop (CPPLL) and an all-digital phase-locked loop (ADPLL). The whole CDR design has been implemented and tested using an Altera® Stratix Development Board. Measurements show a recovered clock peak-to-peak jitter of 10 ns (1% UI) for an input data rate of 1 Mbps.
Keywords :
clocks; digital circuits; digital phase locked loops; network synthesis; ADPLL; CDR circuit design; all-digital clock circuit; all-digital phase-locked loop; analog CPPLL; analog charge-pump based phase-locked loop; bit rate 1 Mbit/s; data recovery circuit; low-to-moderate data rate applications; recovered clock peak-to-peak jitter; time 10 ns; Clocks; Detectors; Jitter; Optical signal processing; Phase locked loops; Radiation detectors; Synchronization; ADPLL; CPPLL; Clock and data recovery; FPGA; TDC; analogy between analog and digital; jitter;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on
Conference_Location :
Beirut
Print_ISBN :
978-1-4577-1845-8
Electronic_ISBN :
978-1-4577-1844-1
DOI :
10.1109/ICECS.2011.6122208
