On the use of VHDL simulation and emulation to derive error rates

This paper proposes a high level technique to inject transient faults in processor-like circuits, and a convenient way to collect and analyze the fault effects in order to cope with them. Faults can be injected in all sensitive parts of the design, such as registers, flip-flops and memory. This approach was implemented and tested in an 8051-like micro-controller VHDL description, emulated in a Virtex FPGA platform. Experimental results of this technique in the standard and in the SEU hardened core show a dramatic reduction in execution time of the experiments, allowing early intervention to protect dedicated cores at low cost.