A novel technique for tuning low voltage linear transconductor

In this paper a novel technique is presented to tune a low voltage linear transconductor. Bias offset is used for tunability and bias currents of cross coupled differential amplifiers are adjusted to minimize third harmonic distortion. Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology is used to simulate the proposed circuit. Simulation results show that for the biasing current of 270 µA (Gm of 215 µS), the circuit exhibits less than −30 dB total third harmonic distortion (HD3) at 1 Vp-p @ 50 MHz and at low voltage supply.