A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform

Author

Clerc, Sylvain ; Abouzeid, Fady ; Argoud, Fabrice ; Kumar, Ajit ; Kumar, Ravindra ; Roche, Philippe

Author_Institution

STMicroelectron., Crolles, France

fYear

2011

fDate

11-14 Dec. 2011

Firstpage

117

Lastpage

120

Abstract

A low cost Ultra Low Voltage design implemented using standard CAD tools with adapted margins is presented. Critical path replica rings have been measured to ensure models validity at ultra-low voltages, on the 0°C to 50°C temperature range. The observed behavior and mismatch compared to CAD simulations enabled us to define the margins to be used for the standard circuit implementation flow. We then derived a cell library focusing our effort on latches and level shifters. A 10k gates, 1k flip-flops demonstrator was designed and measured. Its functional voltage range is extended by 4× down to 0.24V, reducing the dynamic power by a factor 14× versus nominal. Forward Body Biasing and Temperature effect on minimum voltage for both worst die and die population average are reported.

Keywords

CMOS integrated circuits; flip-flops; integrated circuit design; integrated circuit reliability; low-power electronics; CAD tools; CMOS; adapted margins; cell library; critical path replica rings; dynamic power; flip-flops demonstrator; forward body biasing; frame decoder; frequency 1 MHz; frequency 10 MHz; size 40 nm; temperature effect; ultra low voltage circuit design platform; voltage 240 mV; voltage 340 mV; CMOS integrated circuits; Decoding; Design automation; Frequency measurement; Temperature measurement; Timing; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Conference_Location

Beirut

Print_ISBN

978-1-4577-1845-8

Electronic_ISBN

978-1-4577-1844-1

Type

conf

DOI

10.1109/ICECS.2011.6122228

Filename

6122228