Assessing testing techniques for resistive-open defects in nanometer CMOS adders

As we move to smaller CMOS technologies, the need for better testing techniques arises. We investigate the effectiveness of four testing techniques against resistive-open defects. The tests are applied to two adder topologies, namely the quasi-clocked adder and the bridge-style adder. The tests are done under full process variations for technologies down to 16nm. The test techniques based on dynamic power supply current (i_DDT) show superiority for large-feature technologies, but as the technology decreases delay tests appear to be the most effective.