A new FFT concept for efficient VLSI implementation: Part II - Parallel Pipelined Processing

The success of computational science to accurately describe and model the real world has helped to fuel the ever increasing demand for cheap computing power. This paper presents a solution to the FFT´s parallel multiprocessing problem, and involves novel concepts wherein the realization of parallel pipelines and multistage parallel pipelines are possible. The problem resides in defining the mathematical model of the socalled combination phase, in which the concept of representing the discrete Fourier transform (DFT) in terms of its partial DFTs should be well structured to obtain the right mathematical model. The resulting implementation in which r parallel processors operate simultaneously within a single instruction reduces the number of communications phases and the no-operation states (NOP) to their minimum values. The two papers, Part I and II, Butterfly processing element and Parallel pipelined processing, provide a new FFT concept for efficient VLSI implementation.