A novel design methodology for multiplierless filters applied on ΔΣ decimators

This paper presents a novel methodology to design multiplierless digital filters. It is very simple to implement and optimizes the order and the number of adders of the filter. This technique was employed to design two decimators for a 640 MHz-12 bits and a 26 MHz-13 bits Delta Sigma Analog to Digital converters (ΣΔ ADCs). The filters were synthesized in a 65 nm CMOS process. Their power consumption and die are (12.54 mW, 0.075 mm²) for the first decimator and (110.2 μW, 0.051 mm²) for the second. This is very well positioned in the state of art and thus proves the efficiency of the proposed methodology.