• DocumentCode
    2920731
  • Title

    Design of a 3 Bit 20 GS/s ADC in 65 nm CMOS

  • Author

    Ferenci, Damir ; Grozing, Markus ; Berroth, Manfred

  • Author_Institution
    Inst. of Electr. & Opt. Commun. Eng., Univ. of Stuttgart, Stuttgart, Germany
  • fYear
    2009
  • fDate
    12-17 July 2009
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    A 20 GS/s 3 bit flash ADC with an analog input bandwidth of 10 GHz is realized in a 65 nm LP CMOS technology. By employing a fourfold parallelization a high sample rate is achieved, while a large input bandwidth is maintained. Simulations at 20 GS/s exhibit an effective resolution of 2.5 Bits at the Nyquist frequency. The chip area is 5.2 mm2 while the ADC core area is 0.16 mm2.
  • Keywords
    CMOS integrated circuits; CMOS; Nyquist frequency; fourfold parallelization; Bandwidth; CMOS technology; Capacitance; Circuits; Clocks; Frequency synchronization; Optical design; Optical fiber communication; Sampling methods; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D.
  • Conference_Location
    Cork
  • Print_ISBN
    978-1-4244-3733-7
  • Electronic_ISBN
    978-1-4244-3734-4
  • Type

    conf

  • DOI
    10.1109/RME.2009.5201305
  • Filename
    5201305
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2920731