DocumentCode
2920836
Title
Design of a 1.2-V 60 GHz transceiver in a 90nm CMOS RF technology
Author
Simitsakis, Paschalis ; Liolis, Spyros ; Psyllos, Dimitris ; Mountrichas, Lampros ; Sotiriadis, Paul P.
Author_Institution
THETA S.A., Athens, Greece
fYear
2011
fDate
11-14 Dec. 2011
Firstpage
342
Lastpage
345
Abstract
In this paper the design of a high-data-rate transceiver in the 60 GHz band using a QPSK modulation scheme is presented. The channel bandwidth is 1 GHz in order to achieve gigabit Ethernet wireless transmission at 1km distance. The receiver has 66 db of linear controlled gain with a noise figure of 8 dB. The transmitter is capable of delivering -12 dBm of power at the external power amplifier. Both circuits operate under a 1.2 V power supply.
Keywords
CMOS integrated circuits; local area networks; quadrature phase shift keying; radio transceivers; CMOS RF technology; QPSK modulation; frequency 60 GHz; gigabit Ethernet wireless transmission; high-data-rate transceiver; power amplifier; size 90 nm; voltage 1.2 V; Band pass filters; CMOS integrated circuits; Gain; Mixers; Radio frequency; Receivers; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on
Conference_Location
Beirut
Print_ISBN
978-1-4577-1845-8
Electronic_ISBN
978-1-4577-1844-1
Type
conf
DOI
10.1109/ICECS.2011.6122283
Filename
6122283
Link To Document