A novel LV LP CMOS internal topology of CCII+ and its application in current-mode integrated circuits

In this paper we present a novel internal architecture of low-voltage and low-power positive second-generation current conveyor (CCII+). The proposed internal circuit topology, designed in standard CMOS technology (AMS 0.35 ¿m), employs an n-type differential pair as input stage, while a cascoded push-pull configuration implements a very high impedance output stage. A degenerated nMOS common drain topology reduces X node impedance. The choice of internal CCII+ architecture, concerning both its stage architecture and transistor sizes, has been made in the direction of designing a quasi-ideal CCII+ in terms of parasitic components at its terminals. The developed CCII+ operates at low supply voltages of ±1 V with a total power consumption of about 300 ¿W, so it is suitable for general purpose portable applications. It has been also characterized implementing well-known applications, both in time and frequency domains, such as signal processing circuits and impedance simulators.