Title :
FPGA-implementation of high-speed MLP neural network
Author :
Bahoura, Mohammed ; Park, Chan-Wang
Author_Institution :
Dept. of Eng., Univ. du Quebec a Rimouski, Rimouski, QC, Canada
Abstract :
This paper presents a new high-speed FPGA implementation of a pipelined adaptive multilayer perceptron (MLP). The proposed approach is a fully parallel architecture based on the delayed backpropagation algorithm, which permits to reduce the critical path and consequently increases the operating frequency. Results obtained with nonlinear function approximation show that this pipelined parallel architecture is four times faster than the conventional one.
Keywords :
backpropagation; field programmable gate arrays; multilayer perceptrons; neural nets; parallel architectures; FPGA; MLP neural network; critical path reduction; delayed backpropagation algorithm; field programmable gate arrays; nonlinear function approximation; pipelined adaptive multilayer perceptron; pipelined parallel architecture; Artificial neural networks; Backpropagation algorithms; Computer architecture; Delay; Field programmable gate arrays; Neurons; Random access memory;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on
Conference_Location :
Beirut
Print_ISBN :
978-1-4577-1845-8
Electronic_ISBN :
978-1-4577-1844-1
DOI :
10.1109/ICECS.2011.6122304
