Title :
CMOS-compatible structure for voltage-mode multiple-valued logic circuits
Author :
Sendi, Mohammad S Eslampanah ; Sharifkhani, Mohammad ; Sodagar, Amir M.
Author_Institution :
ECE Dept., Sharif Univ. of Technol., Tehran, Iran
Abstract :
This paper presents a low-voltage, CMOS-compatible, voltage-mode structure for multiple-valued logic circuits. Designed based on a simple and straightforward mechanism and operating in the voltage mode, the proposed structure is suitable for low power applications. Design of both a quaternary inverter and a latch circuit based on the proposed structure are also presented. These circuits are designed in a 0.18-μm CMOS technology with a supply voltage of 1.8V, and dissipate 60nW static power for both circuits. Static noise margin of the inverter is 0.22V.
Keywords :
CMOS integrated circuits; CMOS logic circuits; logic gates; low-power electronics; 0.18-μm CMOS technology; CMOS-compatible structure; inverter; latch circuit; low power application; power 60 nW; quaternary inverter; size 0.18 mum; static noise margin; voltage 0.22 V to 1.8 V; voltage-mode multiple-valued logic circuit; CMOS integrated circuits; CMOS technology; Inverters; Latches; Logic gates; Noise; Threshold voltage; MAX circuit; Multiple-valued logic circuit; Quaternary inverter; Quaternary latch; Voltage-mode;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on
Conference_Location :
Beirut
Print_ISBN :
978-1-4577-1845-8
Electronic_ISBN :
978-1-4577-1844-1
DOI :
10.1109/ICECS.2011.6122307
