Title :
Designing variability tolerant logic using evolutionary algorithms
Author :
Hilder, James A. ; Walker, James Alfred ; Tyrrell, Andy M.
Author_Institution :
Univ. of York, York, UK
Abstract :
This paper describes an approach to create novel, robust logic-circuit topologies, using several evolution-inspired techniques over a number of design stages. A library of 2-input logic gates are evolved and optimised for tolerance to the effects of intrinsic variability. Block-level designs are evolved using evolutionary methods (CGP). A method of selecting the optimal gates from the library to fit into the block-level designs to create variability-tolerant circuits is also proposed.
Keywords :
circuit optimisation; evolutionary computation; integrated circuit design; logic design; block-level designs; evolutionary algorithms; intrinsic variability; logic gates; robust logic circuit topology; variability tolerant logic; Algorithm design and analysis; Atomic layer deposition; Design optimization; Evolutionary computation; Fluctuations; Genetic programming; Libraries; Logic design; Semiconductor process modeling; Stochastic processes;
Conference_Titel :
Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D.
Conference_Location :
Cork
Print_ISBN :
978-1-4244-3733-7
Electronic_ISBN :
978-1-4244-3734-4
DOI :
10.1109/RME.2009.5201345
